| base+4 ... base+2          | base             | number of bits             |
| ------ -----------------   | ---------------- | -------------------------- |
| ..xxxx  xxxxxxxxxxxxxxxx   | xnnnxxxxx1111111 | (80+16\*nnn)-bit, nnn!=111 |
| {ops}{Pred}{Reg}{VL Block} | VBLOCK Prefix    |                            |

A suitable prefix, which fits the Expanded Instruction-Length encoding
for "(80 + 16 times instruction-length)", as defined in Section 1.5
of the RISC-V ISA, is as follows:

| 15    | 14:12 | 11:10 | 9:8   | 7    | 6:0     |
| -     | ----- | ----- | ----- | ---  | ------- |
| vlset | 16xil | pplen | rplen | mode | 1111111 |

The VL/MAXVL/SubVL Block format:

| 31-30 | 29:28 | 27:22  | 21:17  | 16  | comment |
| -     | ----- | ------ | ------ | -   | -|
| 0     | SubVL | VLdest | VLimm  | 0   | |
| 0     | SubVL | MVLimm | VLreg  | 1   | VLdest=t0 |
| 1     | SubVL | VLdest | VLimm  | imm | VL & MVL, bits 16-21 |