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Test resuming from a trigger.
[riscv-tests.git]
/
debug
/
programs
/
trigger.S
diff --git
a/debug/programs/trigger.S
b/debug/programs/trigger.S
index e5dfa6745d62af006782bf99fd179cc8f4e3880e..13f044978c830ecf31e72dfecc14503ccf4ef7db 100644
(file)
--- a/
debug/programs/trigger.S
+++ b/
debug/programs/trigger.S
@@
-1,13
+1,13
@@
-#include "
../../env/
encoding.h"
+#include "encoding.h"
-#undef MCONTROL_TYPE
-#undef MCONTROL_DMODE
-#ifdef __riscv64
-# define MCONTROL_TYPE (0xfU<<((64)-4))
-# define MCONTROL_DMODE (1U<<((64)-5))
+#if XLEN == 64
+# define LREG ld
+# define SREG sd
+# define REGBYTES 8
#else
#else
-# define MCONTROL_TYPE (0xfU<<((32)-4))
-# define MCONTROL_DMODE (1U<<((32)-5))
+# define LREG lw
+# define SREG sw
+# define REGBYTES 4
#endif
.global main
#endif
.global main
@@
-17,68
+17,84
@@
main:
la a0, data
li t0, 0
la a0, data
li t0, 0
+just_before_read_loop:
li t2, 16
read_loop:
lw t1, 0(a0)
li t2, 16
read_loop:
lw t1, 0(a0)
- addi
a0, a0, 4
+ addi
t1, t1, 1
addi t0, t0, 1
addi t0, t0, 1
+read_again:
+ lw t1, 0(a0)
+ addi a0, a0, 4
blt t0, t2, read_loop
la a0, data
blt t0, t2, read_loop
la a0, data
- li t0, 0
+just_before_write_loop:
+ li t0, 1
write_loop:
write_loop:
- addi t0, t0, 1
sw t0, 0(a0)
sw t0, 0(a0)
+ addi t0, t0, 1
addi a0, a0, 4
blt t0, t2, write_loop
j main_exit
addi a0, a0, 4
blt t0, t2, write_loop
j main_exit
-write_valid:
+write_store_trigger:
+ li a0, (1<<6) | (1<<1)
+ li a1, 0xdeadbee0
+ jal write_triggers
+ la a0, data
+ jal read_triggers
+
+write_load_trigger:
+ li a0, (1<<6) | (1<<0)
+ li a1, 0xfeedac00
+ jal write_triggers
+ la a0, data
+ jal read_triggers
+
+// Clear triggers so the next test can use them.
+clear_triggers:
+ li a0, 0
+ jal write_triggers
+
+main_exit:
+ li a0, 0
+ j _exit
+
+write_triggers:
+ // a0: value to write to each tdata1
+ // a1: value to write to each tdata2
li t0, 0
li t0, 0
- li t2, MCONTROL_DMODE
- li t3, MCONTROL_TYPE
-write_valid_loop:
+2:
csrw CSR_TSELECT, t0
csrr t1, CSR_TSELECT
csrw CSR_TSELECT, t0
csrr t1, CSR_TSELECT
- bne t0, t1,
main_exit
+ bne t0, t1,
1f
addi t0, t0, 1
addi t0, t0, 1
- csrr t1, CSR_TDATA1
- and t4, t1, t3
- beqz t4, main_error # type is 0
- and t1, t1, t2
- bnez t1, write_valid_loop
- # Found an entry with dmode=0
- csrw CSR_TDATA1, zero # this should succeed
+ csrw CSR_TDATA2, a1
+ csrw CSR_TDATA1, a0
+ j 2b
+1: ret
-write_invalid:
+read_triggers:
+ // a0: address where data should be written
li t0, 0
li t0, 0
- li t2, MCONTROL_DMODE
- li t3, MCONTROL_TYPE
-write_invalid_loop:
+2:
csrw CSR_TSELECT, t0
csrr t1, CSR_TSELECT
csrw CSR_TSELECT, t0
csrr t1, CSR_TSELECT
- bne t0, t1,
main_exit
+ bne t0, t1,
1f
addi t0, t0, 1
csrr t1, CSR_TDATA1
addi t0, t0, 1
csrr t1, CSR_TDATA1
- and t4, t1, t3
- beqz t4, main_error # type is 0
- and t1, t1, t2
- beqz t1, write_invalid_loop
- # Found an entry with dmode=1
-write_invalid_illegal:
- csrw CSR_TDATA1, zero # this should fail
-
-
-main_exit:
- li a0, 0
- j _exit
-
-main_error:
- li a0, 1
- j _exit
+ SREG t1, 0(a0)
+ csrr t1, CSR_TDATA2
+ SREG t1, REGBYTES(a0)
+ addi a0, a0, 2*REGBYTES
+ j 2b
+1: SREG zero, 0(a0)
+ ret
.data
.data
+ .align 3
data: .word 0x40
.word 0x41
.word 0x42
data: .word 0x40
.word 0x41
.word 0x42