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Make HiFive1 testing (mostly) work again
[riscv-tests.git]
/
debug
/
targets
/
HiFive1
/
openocd.cfg
diff --git
a/debug/targets/HiFive1/openocd.cfg
b/debug/targets/HiFive1/openocd.cfg
index 72a54469d8664b936337d62c8b9eb9ff642d84ab..5bde59bb0a26f3174a666e35e5321d239d418421 100644
(file)
--- a/
debug/targets/HiFive1/openocd.cfg
+++ b/
debug/targets/HiFive1/openocd.cfg
@@
-14,10
+14,13
@@
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1 -rtos riscv
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1
+#-rtos riscv
flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME
init
#reset
halt
flash protect 0 64 last off
flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME
init
#reset
halt
flash protect 0 64 last off
+
+echo "Ready for Remote Connections"