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Make the debug tests aware of multicore.
[riscv-tests.git]
/
debug
/
targets
/
SiFive
/
Freedom
/
U500Sim.py
diff --git
a/debug/targets/SiFive/Freedom/U500Sim.py
b/debug/targets/SiFive/Freedom/U500Sim.py
index 62bc8278ab6efd20f30e9ce8c324883aab89d5a1..5c500c4842c7a6009a5dca06576d72a19843a133 100644
(file)
--- a/
debug/targets/SiFive/Freedom/U500Sim.py
+++ b/
debug/targets/SiFive/Freedom/U500Sim.py
@@
-1,14
+1,17
@@
import targets
import testlib
import targets
import testlib
-class U500
Sim(targets.Targe
t):
+class U500
Hart(targets.Har
t):
xlen = 64
xlen = 64
- timeout_sec = 6000
ram = 0x80000000
ram_size = 256 * 1024 * 1024
instruction_hardware_breakpoint_count = 2
ram = 0x80000000
ram_size = 256 * 1024 * 1024
instruction_hardware_breakpoint_count = 2
- openocd_config_path = "Freedom.cfg"
link_script_path = "Freedom.lds"
link_script_path = "Freedom.lds"
- def create(self):
+class U500Sim(Target):
+ timeout_sec = 6000
+ openocd_config_path = "Freedom.cfg"
+ harts = [U500Hart()]
+
+ def target(self):
return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)