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Give these sim targets a chance of passing.
[riscv-tests.git]
/
debug
/
targets
/
SiFive
/
Freedom
/
U500Sim.py
diff --git
a/debug/targets/SiFive/Freedom/U500Sim.py
b/debug/targets/SiFive/Freedom/U500Sim.py
index 76489602bc96cedc99c1e9ce67152125736dda01..62bc8278ab6efd20f30e9ce8c324883aab89d5a1 100644
(file)
--- a/
debug/targets/SiFive/Freedom/U500Sim.py
+++ b/
debug/targets/SiFive/Freedom/U500Sim.py
@@
-1,4
+1,7
@@
-class U500Sim(Target):
+import targets
+import testlib
+
+class U500Sim(targets.Target):
xlen = 64
timeout_sec = 6000
ram = 0x80000000
xlen = 64
timeout_sec = 6000
ram = 0x80000000
@@
-7,5
+10,5
@@
class U500Sim(Target):
openocd_config_path = "Freedom.cfg"
link_script_path = "Freedom.lds"
openocd_config_path = "Freedom.cfg"
link_script_path = "Freedom.lds"
- def
target
(self):
+ def
create
(self):
return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)