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Use `gdb_report_register_access_error enable`
[riscv-tests.git]
/
debug
/
targets
/
SiFive
/
HiFive1.cfg
diff --git
a/debug/targets/SiFive/HiFive1.cfg
b/debug/targets/SiFive/HiFive1.cfg
index 5bde59bb0a26f3174a666e35e5321d239d418421..333c82e4706dd1eca8393180ca731ffe6dd7276b 100644
(file)
--- a/
debug/targets/SiFive/HiFive1.cfg
+++ b/
debug/targets/SiFive/HiFive1.cfg
@@
-17,6
+17,13
@@
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1
#-rtos riscv
$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1
#-rtos riscv
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+# Expose an unimplemented CSR so we can test non-existent register access
+# behavior.
+riscv expose_csrs 2288
+
flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME
init
#reset
flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME
init
#reset