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Give these sim targets a chance of passing.
[riscv-tests.git]
/
debug
/
testlib.py
diff --git
a/debug/testlib.py
b/debug/testlib.py
index debe3685af30182c68b7cda555917103e09e9b4a..597c69bd19cf93931349d43e5b1973323f624043 100644
(file)
--- a/
debug/testlib.py
+++ b/
debug/testlib.py
@@
-116,6
+116,8
@@
class Spike(object):
return self.process.wait(*args, **kwargs)
class VcsSim(object):
return self.process.wait(*args, **kwargs)
class VcsSim(object):
+ logname = "simv.log"
+
def __init__(self, sim_cmd=None, debug=False):
if sim_cmd:
cmd = shlex.split(sim_cmd)
def __init__(self, sim_cmd=None, debug=False):
if sim_cmd:
cmd = shlex.split(sim_cmd)
@@
-125,10
+127,10
@@
class VcsSim(object):
if debug:
cmd[0] = cmd[0] + "-debug"
cmd += ["+vcdplusfile=output/gdbserver.vpd"]
if debug:
cmd[0] = cmd[0] + "-debug"
cmd += ["+vcdplusfile=output/gdbserver.vpd"]
- logfile = open(
"simv.log"
, "w")
+ logfile = open(
self.logname
, "w")
logfile.write("+ %s\n" % " ".join(cmd))
logfile.flush()
logfile.write("+ %s\n" % " ".join(cmd))
logfile.flush()
- listenfile = open(
"simv.log"
, "r")
+ listenfile = open(
self.logname
, "r")
listenfile.seek(0, 2)
self.process = subprocess.Popen(cmd, stdin=subprocess.PIPE,
stdout=logfile, stderr=logfile)
listenfile.seek(0, 2)
self.process = subprocess.Popen(cmd, stdin=subprocess.PIPE,
stdout=logfile, stderr=logfile)