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add fp add elwidth single-precision test
[riscv-tests.git]
/
isa
/
macros
/
simplev
/
sv_test_macros.h
diff --git
a/isa/macros/simplev/sv_test_macros.h
b/isa/macros/simplev/sv_test_macros.h
index 0395755164b8e89e89f71f987c8e93f8e1608e02..6c671df0e17cf5851238ee442480cba5ba435ba1 100644
(file)
--- a/
isa/macros/simplev/sv_test_macros.h
+++ b/
isa/macros/simplev/sv_test_macros.h
@@
-41,6
+41,10
@@
la x1, from; \
fld reg, offs(x1)
la x1, from; \
fld reg, offs(x1)
+#define SV_FLW_DATA( reg, from, offs ) \
+ la x1, from; \
+ flw reg, offs(x1)
+
#define TEST_SV_IMM( reg, imm ) \
li t6, ((imm) & 0xffffffffffffffff); \
bne reg, t6, fail
#define TEST_SV_IMM( reg, imm ) \
li t6, ((imm) & 0xffffffffffffffff); \
bne reg, t6, fail
@@
-54,6
+58,15
@@
fmv.x.d x2, freg; \
bne x2, x1, fail
fmv.x.d x2, freg; \
bne x2, x1, fail
+#define TEST_SV_FW( flags, freg, from, offs ) \
+ fsflags x2, x0; \
+ li x1, flags; \
+ bne x2, x1, fail; \
+ la x1, from; \
+ lw x1, offs(x1); \
+ fmv.x.s x2, freg; \
+ bne x2, x1, fail
+
#define SV_W_DFLT 0
#define SV_W_8BIT 1
#define SV_W_16BIT 2
#define SV_W_DFLT 0
#define SV_W_8BIT 1
#define SV_W_16BIT 2