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add sv_add_elwidth unit test
[riscv-tests.git]
/
isa
/
macros
/
simplev
/
sv_test_macros.h
diff --git
a/isa/macros/simplev/sv_test_macros.h
b/isa/macros/simplev/sv_test_macros.h
index a480bd6648b763fef1c52adaa6363ba534413c89..dccb7846967d61ce8659980a7bb4c6ba0915e152 100644
(file)
--- a/
isa/macros/simplev/sv_test_macros.h
+++ b/
isa/macros/simplev/sv_test_macros.h
@@
-12,11
+12,15
@@
csrrw x0, 0x4c8, x1
#define SET_SV_2CSRS( c1, c2 ) \
csrrw x0, 0x4c8, x1
#define SET_SV_2CSRS( c1, c2 ) \
- li x1, c1 | ((c2)<<16); \
+ li x1, c1 | ((c2)<<16U); \
+ csrrw x0, 0x4c0, x1
+
+#define SET_SV_3CSRS( c1, c2 , c3 ) \
+ li x1, c1 | ((c2)<<16U) | ((c3)<<32U); \
csrrw x0, 0x4c0, x1
#define SET_SV_2PREDCSRS( c1, c2 ) \
csrrw x0, 0x4c0, x1
#define SET_SV_2PREDCSRS( c1, c2 ) \
- li x1, c1 | ((c2)<<16); \
+ li x1, c1 | ((c2)<<16
U
); \
csrrw x0, 0x4c8, x1
#define CLR_SV_CSRS( ) csrrw x0, 0x4c0, 0
csrrw x0, 0x4c8, x1
#define CLR_SV_CSRS( ) csrrw x0, 0x4c0, 0
@@
-29,12
+33,16
@@
la x1, from; \
lw reg, offs(x1)
la x1, from; \
lw reg, offs(x1)
+#define SV_LDD_DATA( reg, from, offs ) \
+ la x1, from; \
+ ld reg, offs(x1)
+
#define SV_FLD_DATA( reg, from, offs ) \
la x1, from; \
fld reg, offs(x1)
#define TEST_SV_IMM( reg, imm ) \
#define SV_FLD_DATA( reg, from, offs ) \
la x1, from; \
fld reg, offs(x1)
#define TEST_SV_IMM( reg, imm ) \
- li t6,
imm
; \
+ li t6,
((imm) & 0xffffffffffffffff)
; \
bne reg, t6, fail
#define TEST_SV_FD( flags, freg, from, offs ) \
bne reg, t6, fail
#define TEST_SV_FD( flags, freg, from, offs ) \