when muxwidth == 1 output pin directly

[pinmux.git] / src / bsv / actual_pinmux.py

diff --git a/src/bsv/actual_pinmux.py b/src/bsv/actual_pinmux.py
index 58e204002fb857f2b8e38c376906a7f157e7b78b..7156fd154af5d8edbadbfbcdad481f6e309568bf 100644 (file)
--- a/src/bsv/actual_pinmux.py
+++ b/src/bsv/actual_pinmux.py
@@ -24,13 +24,6 @@ dedicated_wire = '''
 digits = maketrans('0123456789', ' ' * 10)  # delete space later
 
 
 digits = maketrans('0123456789', ' ' * 10)  # delete space later
 
 

-def get_cell_bit_width(p):
-    max_num_cells = 0
-    for cell in p.muxed_cells:
-        max_num_cells = max(len(cell) - 1, max_num_cells)
-    return int(math.log(max_num_cells + 1, 2))
-
-

 def cn(idx):  # idx is an integer
     return "cell%s_mux" % str(idx)
 
 def cn(idx):  # idx is an integer
     return "cell%s_mux" % str(idx)
 


@@ -68,6 +61,7 @@ def fmt(ifaces, cells, idx, suffix=None):
         cell = cells[idx]
     else:
         cell = ''
         cell = cells[idx]
     else:
         cell = ''

+    #print "fmt", idx, cells, cell

     if not cell:
         return 'val0'
     temp = transfn(cell)
     if not cell:
         return 'val0'
     temp = transfn(cell)


@@ -75,8 +69,8 @@ def fmt(ifaces, cells, idx, suffix=None):
     if x == 'input':
         return 'val0'  # inputs don't get passed through to the out mux
     if suffix == '_outen' and x == 'out':
     if x == 'input':
         return 'val0'  # inputs don't get passed through to the out mux
     if suffix == '_outen' and x == 'out':

-        return "wr%s%s" % (cells[1], suffix or '') # USE GPIO FOR SELECTION
-    if x == 'out': # sigh hack, should be using interface_decl
+        return "wr%s%s" % (cells[1], suffix or '')  # USE GPIO FOR SELECTION
+    if x == 'out':  # sigh hack, should be using interface_decl

         suffix = ''
     return "wr%s%s" % (cell, suffix or '')
 
         suffix = ''
     return "wr%s%s" % (cell, suffix or '')
 


@@ -110,18 +104,22 @@ def mkmux(p, ifaces, cell, suffix, outenmode):
         multiple inputs and, based on an "address" routes
         a given indexed input through to the (one) output
     """
         multiple inputs and, based on an "address" routes
         a given indexed input through to the (one) output
     """

+    cellnum = cell[0]

     comment = 'outen' if outenmode else 'output'
     fmtstr = "\t\t\twr%s==%d?%s:%s\n"  # mux-selector format
     ret = ''
     comment = 'outen' if outenmode else 'output'
     fmtstr = "\t\t\twr%s==%d?%s:%s\n"  # mux-selector format
     ret = ''

-    ret += "      // %s muxer for cell idx %s\n" % (comment, cell[0])
-    ret += "      %s%s=\n" % (cn(cell[0]), suffix)
-    for i in range(
-            0, (1 << p.cell_bitwidth) - 1):  # full mux range (minus 1)
-        comment = mkcomment(ifaces, cell, i, outenmode)
-        cf = fmt(ifaces, cell, i, suffix)
-        ret += fmtstr % (cn(cell[0]), i, cf, comment)
-    comment = mkcomment(ifaces, cell, i + 1, outenmode)
-    ret += "\t\t\t" + fmt(ifaces, cell, i + 1, suffix)  # last line
+    ret += "      // %s muxer for cell idx %s\n" % (comment, cellnum)
+    ret += "      %s%s=\n" % (cn(cellnum), suffix)
+    i = 0
+    mwid = p.get_muxwidth(cellnum)
+    if mwid > 1:
+        for i in range(0, mwid - 1):  # full mux range (minus 1)
+            comment = mkcomment(ifaces, cell, i, outenmode)
+            cf = fmt(ifaces, cell, i, suffix)
+            ret += fmtstr % (cn(cell[0]), i, cf, comment)
+        i += 1
+    comment = mkcomment(ifaces, cell, i, outenmode)
+    ret += "\t\t\t" + fmt(ifaces, cell, i, suffix)  # last line

     ret += ";%s\n" % comment
 
     return ret
     ret += ";%s\n" % comment
 
     return ret


@@ -147,11 +145,15 @@ def init(p, ifaces):
         the last one, and we do not want the "default" (last line)
         to be the output.
     """
         the last one, and we do not want the "default" (last line)
         to be the output.
     """

-    p.cell_bitwidth = get_cell_bit_width(p)

     p.pinmux = ' '
     global dedicated_wire
     for cell in p.muxed_cells:
 
     p.pinmux = ' '
     global dedicated_wire
     for cell in p.muxed_cells:
 

+        cellidx = cell[0]
+
+        p.pinmux += "      // --------------------\n"
+        p.pinmux += "      // ----- cell %s -----\n\n" % (cellidx)
+

         # first do the outputs
         p.pinmux += mkmux(p, ifaces, cell, '_out', False)
         p.pinmux += "\n"
         # first do the outputs
         p.pinmux += mkmux(p, ifaces, cell, '_out', False)
         p.pinmux += "\n"


@@ -167,26 +169,23 @@ def init(p, ifaces):
         # since the interfaces are always standard and cannot change from
         # user-to-user. Plus this also reduces human-error as well :)
         p.pinmux += "\n"
         # since the interfaces are always standard and cannot change from
         # user-to-user. Plus this also reduces human-error as well :)
         p.pinmux += "\n"

-        p.pinmux += "      // priority-in-muxer for cell idx %s\n" % (cell[0])
+        p.pinmux += "      // priority-in-muxer for cell idx %s\n" % (cellidx)

         for i in range(0, len(cell) - 1):
             cname = cell[i + 1]
             if not cname:  # skip blank entries, no need to test
                 continue
             temp = transfn(cname)
             x = ifaces.getifacetype(temp)
         for i in range(0, len(cell) - 1):
             cname = cell[i + 1]
             if not cname:  # skip blank entries, no need to test
                 continue
             temp = transfn(cname)
             x = ifaces.getifacetype(temp)

-            #print (cname, temp, x)
+            print (cname, temp, x)

             assert x is not None, "ERROR: The signal : " + \
                 str(cname) + \
                 " of pinmap.txt isn't present \nin the current" + \
                 " dictionary. Update dictionary or fix-typo."
             assert x is not None, "ERROR: The signal : " + \
                 str(cname) + \
                 " of pinmap.txt isn't present \nin the current" + \
                 " dictionary. Update dictionary or fix-typo."

-            if x == "input":
-                p.pinmux += \
-                    mux_wire.format(cell[0], i, "wr" + cname) + "\n"
-            elif x == "inout":
-                p.pinmux += \
-                    mux_wire.format(cell[0], i, "wr" + cname +
-                                                "_in") + "\n"
-    # ============================================================ #
+            bwid = p.get_muxbitwidth(cellidx)
+            if bwid > 0:
+                muxcell(p, cname, x, cell, i)
+            else:
+                dedcell(p, x, cell)

 
     # ==================  Logic for dedicated pins ========= #
     p.pinmux += "\n      /*=========================================*/\n"
 
     # ==================  Logic for dedicated pins ========= #
     p.pinmux += "\n      /*=========================================*/\n"


@@ -197,12 +196,20 @@ def init(p, ifaces):
         temp = transfn(cell[1])
         x = ifaces.getifacetype(temp)
         #print cell, temp, x
         temp = transfn(cell[1])
         x = ifaces.getifacetype(temp)
         #print cell, temp, x

-        if x == "input":
-            p.pinmux += \
-                dedicated_wire.format(cell[0], "wr" + cell[1]) + "\n"
-        elif x == "inout":
-            p.pinmux += \
-                dedicated_wire.format(cell[0], "wr" + cell[1] + "_in") + "\n"
-        else:
-            p.pinmux += "\n"
-    # =======================================================#
+        dedcell(p, x, cell)
+
+def muxcell(p, cname, x, cell, i):
+    if x == "input":
+        p.pinmux += \
+            mux_wire.format(cell[0], i, "wr" + cname) + "\n"
+    elif x == "inout":
+        p.pinmux += \
+            mux_wire.format(cell[0], i, "wr" + cname +
+                                        "_in") + "\n"
+def dedcell(p, x, cell):
+    if x == "input":
+        p.pinmux += \
+            dedicated_wire.format(cell[0], "wr" + cell[1]) + "\n"
+    elif x == "inout":
+        p.pinmux += \
+            dedicated_wire.format(cell[0], "wr" + cell[1] + "_in") + "\n"