- `ifdef DMA
- //rule to connect all interrupt lines to the DMA
- //All the interrupt lines to DMA are active HIGH. For peripherals that are not connected, or those which do not
- //generate an interrupt (like TCM), drive a constant 1 on the corresponding interrupt line.
- `ifdef I2C1 SyncBitIfc#(Bit#(1)) i2c1_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
- `ifdef I2C0 SyncBitIfc#(Bit#(1)) i2c0_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
- `ifdef QSPI1 SyncBitIfc#(Bit#(1)) qspi1_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
- `ifdef QSPI0 SyncBitIfc#(Bit#(1)) qspi0_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
- `ifdef UART0 SyncBitIfc#(Bit#(1)) uart0_interrupt <-mkSyncBitToCC(uart_clock,uart_reset); `endif
- rule synchronize_i2c_interrupts;
- `ifdef I2C1 i2c1_interrupt.send(slow_peripherals.i2c1_isint); `endif
- `ifdef I2C0 i2c0_interrupt.send(slow_peripherals.i2c0_isint); `endif
- endrule
- rule synchronize_qspi_interrupts;
- `ifdef QSPI0 qspi0_interrupt.send(slow_peripherals.qspi0_isint); `endif
- `ifdef QSPI1 qspi1_interrupt.send(slow_peripherals.qspi1_isint); `endif
- endrule
- rule synchronize_uart0_interrupt;
- `ifdef UART0 uart0_interrupt.send(slow_peripherals.uart0_intr); `endif
- endrule
- rule rl_connect_interrupt_to_DMA;
- Bit#(12) lv_interrupt_to_DMA= {{'d-1,
- `ifdef I2C1 i2c1_interrupt.read `else 1'b1 `endif ,
- `ifdef I2C0 i2c0_interrupt.read `else 1'b1 `endif ,
- `ifdef QSPI1 qspi1_interrupt.read `else 1'b1 `endif ,
- 1'b1,
- `ifdef QSPI0 qspi0_interrupt.read `else 1'b1 `endif ,
- 1'b1,1'b0,
- `ifdef UART0 uart0_interrupt.read `else 1'b1 `endif }};
- dma.interrupt_from_peripherals(lv_interrupt_to_DMA);
- endrule
- `endif
+ `ifdef DMA
+ // rule to connect all interrupt lines to the DMA
+ // All the interrupt lines to DMA are active
+ // HIGH. For peripherals that are not connected,
+ // or those which do not
+ // generate an interrupt (like TCM), drive a constant 1
+ // on the corresponding interrupt line.
+{7}
+ `endif