+ def get_clk_spc(self, ctype):
+ if ctype == 'slow':
+ return "sp_clock, sp_reset"
+ else:
+ return "core_clock, core_reset"
+
+ def _mk_clk_vcon(self, name, count, ctype, typ, pname, bitspec):
+ ck = self.get_clock_reset(name, count)
+ if ck == PBase.get_clock_reset(self, name, count):
+ return ''
+ if ctype == 'slow':
+ spc = self.get_clk_spc(ctype)
+ else:
+ spc = ck
+ ck = self.get_clk_spc(ctype)
+ template = """\
+Ifc_sync#({0}) {1}_sync <-mksyncconnection(
+ {2}, {3});"""
+
+ n_ = "{0}{1}".format(name, count)
+ n_ = '{0}_{1}'.format(n_, pname)
+ if typ == 'in' or typ == 'inout':
+ ck, spc = spc, ck
+ return template.format(bitspec, n_, ck, spc)
+