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gpio: Use Synchronizer for the inputs
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
gpio
/
GPIO.scala
diff --git
a/src/main/scala/devices/gpio/GPIO.scala
b/src/main/scala/devices/gpio/GPIO.scala
index 4884227c49027a712bba6d6951cce768c1e356f1..d4cd24e07d58541f1b6a08fa88cdb907072485e9 100644
(file)
--- a/
src/main/scala/devices/gpio/GPIO.scala
+++ b/
src/main/scala/devices/gpio/GPIO.scala
@@
-4,6
+4,7
@@
package sifive.blocks.devices.gpio
import Chisel._
import sifive.blocks.devices.pinctrl.{PinCtrl, Pin, BasePin, EnhancedPin, EnhancedPinCtrl}
import freechips.rocketchip.config.Parameters
import Chisel._
import sifive.blocks.devices.pinctrl.{PinCtrl, Pin, BasePin, EnhancedPin, EnhancedPinCtrl}
import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.util.SynchronizerShiftReg
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util.{AsyncResetRegVec, GenericParameterizedBundle}
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util.{AsyncResetRegVec, GenericParameterizedBundle}
@@
-34,6
+35,14
@@
object IOFCtrl {
// for the IOF
class IOFPin extends Pin {
val o = new IOFCtrl().asOutput
// for the IOF
class IOFPin extends Pin {
val o = new IOFCtrl().asOutput
+
+ def default(): Unit = {
+ this.o.oval := Bool(false)
+ this.o.oe := Bool(false)
+ this.o.ie := Bool(false)
+ this.o.valid := Bool(false)
+ }
+
def inputPin(pue: Bool = Bool(false) /*ignored*/): Bool = {
this.o.oval := Bool(false)
this.o.oe := Bool(false)
def inputPin(pue: Bool = Bool(false) /*ignored*/): Bool = {
this.o.oval := Bool(false)
this.o.oe := Bool(false)
@@
-53,7
+62,7
@@
class IOFPin extends Pin {
// Connect both the i and o side of the pin,
// and drive the valid signal for the IOF.
// Connect both the i and o side of the pin,
// and drive the valid signal for the IOF.
-object
GPIO
PinToIOF {
+object
Base
PinToIOF {
def apply(pin: BasePin, iof: IOFPin): Unit = {
iof <> pin
iof.o.valid := Bool(true)
def apply(pin: BasePin, iof: IOFPin): Unit = {
iof <> pin
iof.o.valid := Bool(true)
@@
-74,7
+83,7
@@
class GPIOPortIO(c: GPIOParams) extends GenericParameterizedBundle(c) {
// It would be better if the IOF were here and
// we could do the pinmux inside.
trait HasGPIOBundleContents extends Bundle {
// It would be better if the IOF were here and
// we could do the pinmux inside.
trait HasGPIOBundleContents extends Bundle {
-
val
params: GPIOParams
+
def
params: GPIOParams
val port = new GPIOPortIO(params)
}
val port = new GPIOPortIO(params)
}
@@
-98,7
+107,7
@@
trait HasGPIOModuleContents extends Module with HasRegMap {
// Synchronize Input to get valueReg
val inVal = Wire(UInt(0, width=c.width))
inVal := Vec(io.port.pins.map(_.i.ival)).asUInt
// Synchronize Input to get valueReg
val inVal = Wire(UInt(0, width=c.width))
inVal := Vec(io.port.pins.map(_.i.ival)).asUInt
- val inSyncReg = S
hiftRegister(inVal, 3
)
+ val inSyncReg = S
ynchronizerShiftReg(inVal, 3, Some("inSyncReg")
)
val valueReg = Reg(init = UInt(0, c.width), next = inSyncReg)
// Interrupt Configuration
val valueReg = Reg(init = UInt(0, c.width), next = inSyncReg)
// Interrupt Configuration