-trait HasPeripheryI2CBundle extends HasTopLevelNetworksBundle{
- val outer: HasPeripheryI2C
- val i2cs = Vec(outer.i2cParams.size, new I2CPort)
+trait HasPeripheryI2CBundle {
+ val i2cs: Vec[I2CPort]
+
+ def toGPIOPins(syncStages: Int = 0): Seq[I2CGPIOPort] = i2cs.map { i =>
+ val pin = Module(new I2CGPIOPort(syncStages))
+ pin.io.i2c <> i
+ pin
+ }