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GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they...
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
i2c
/
I2CPeriphery.scala
diff --git
a/src/main/scala/devices/i2c/I2CPeriphery.scala
b/src/main/scala/devices/i2c/I2CPeriphery.scala
index a79f94c5588af415ad3797aad6409830e9b802dc..d9c3ff4085d3aa515f1dcc309dd6eed5d77d8002 100644
(file)
--- a/
src/main/scala/devices/i2c/I2CPeriphery.scala
+++ b/
src/main/scala/devices/i2c/I2CPeriphery.scala
@@
-22,8
+22,8
@@
trait HasPeripheryI2C extends HasSystemNetworks {
trait HasPeripheryI2CBundle {
val i2cs: Vec[I2CPort]
trait HasPeripheryI2CBundle {
val i2cs: Vec[I2CPort]
- def toGPIOPins(
dummy: Int = 1
): Seq[I2CGPIOPort] = i2cs.map { i =>
- val pin = Module(new I2CGPIOPort)
+ def toGPIOPins(
syncStages: Int = 0
): Seq[I2CGPIOPort] = i2cs.map { i =>
+ val pin = Module(new I2CGPIOPort
(syncStages)
)
pin.io.i2c <> i
pin
}
pin.io.i2c <> i
pin
}