projects
/
sifive-blocks.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
Merge remote-tracking branch 'origin/master' into typed_pad_ctrl
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
i2c
/
I2CPeriphery.scala
diff --git
a/src/main/scala/devices/i2c/I2CPeriphery.scala
b/src/main/scala/devices/i2c/I2CPeriphery.scala
index 1cc927f46adf7b5243c76d31c23c0f703e4ac295..f4394073eceb3784414b66a756dea9c184f2f7a0 100644
(file)
--- a/
src/main/scala/devices/i2c/I2CPeriphery.scala
+++ b/
src/main/scala/devices/i2c/I2CPeriphery.scala
@@
-19,20
+19,14
@@
trait HasPeripheryI2C extends HasPeripheryBus {
}
trait HasPeripheryI2CBundle {
}
trait HasPeripheryI2CBundle {
- val i2cs: Vec[I2CPort]
-
- def I2CtoGPIOPins(syncStages: Int = 0): Seq[I2CPinsIO] = i2cs.map { i =>
- val pins = Module(new I2CGPIOPort(syncStages))
- pins.io.i2c <> i
- pins.io.pins
- }
+ val i2c: Vec[I2CPort]
}
trait HasPeripheryI2CModuleImp extends LazyMultiIOModuleImp with HasPeripheryI2CBundle {
val outer: HasPeripheryI2C
}
trait HasPeripheryI2CModuleImp extends LazyMultiIOModuleImp with HasPeripheryI2CBundle {
val outer: HasPeripheryI2C
- val i2c
s
= IO(Vec(outer.i2cParams.size, new I2CPort))
+ val i2c = IO(Vec(outer.i2cParams.size, new I2CPort))
- (i2c
s
zip outer.i2c).foreach { case (io, device) =>
+ (i2c zip outer.i2c).foreach { case (io, device) =>
io <> device.module.io.port
}
}
io <> device.module.io.port
}
}