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i2c, uart: Use Synchronizer primitives for the inputs
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
i2c
/
I2CPins.scala
diff --git
a/src/main/scala/devices/i2c/I2CPins.scala
b/src/main/scala/devices/i2c/I2CPins.scala
index 8e17765b908a48511db73f27acd0b1d953b5dbad..2e294238d0b5286b1c50a2407aa1a8d5331f0f08 100644
(file)
--- a/
src/main/scala/devices/i2c/I2CPins.scala
+++ b/
src/main/scala/devices/i2c/I2CPins.scala
@@
-3,9
+3,8
@@
package sifive.blocks.devices.i2c
import Chisel._
import chisel3.experimental.{withClockAndReset}
import Chisel._
import chisel3.experimental.{withClockAndReset}
+import freechips.rocketchip.util.SynchronizerShiftRegInit
import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
-import sifive.blocks.util.ShiftRegisterInit
-
class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
@@
-15,15
+14,15
@@
class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
override def cloneType: this.type =
this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
override def cloneType: this.type =
this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
- def from
I2C
Port(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = {
+ def fromPort(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = {
withClockAndReset(clock, reset) {
scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
scl.o.oe := i2c.scl.oe
withClockAndReset(clock, reset) {
scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
scl.o.oe := i2c.scl.oe
- i2c.scl.in := S
hiftRegisterInit(scl.i.ival, syncStages,
Bool(true))
+ i2c.scl.in := S
ynchronizerShiftRegInit(scl.i.ival, syncStages, init =
Bool(true))
sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
sda.o.oe := i2c.sda.oe
sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
sda.o.oe := i2c.sda.oe
- i2c.sda.in := S
hiftRegisterInit(sda.i.ival, syncStages,
Bool(true))
+ i2c.sda.in := S
ynchronizerShiftRegInit(sda.i.ival, syncStages, init =
Bool(true))
}
}
}
}
}
}