projects
/
sifive-blocks.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
spi: Make memory mapped interface depth a parameter
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
spi
/
SPIPeriphery.scala
diff --git
a/src/main/scala/devices/spi/SPIPeriphery.scala
b/src/main/scala/devices/spi/SPIPeriphery.scala
index 6e586473bb0c021819b07804f6944a204145ca19..595ffc3527e18b08ccd884b7d15ec349771fb4e5 100644
(file)
--- a/
src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/
src/main/scala/devices/spi/SPIPeriphery.scala
@@
-43,7
+43,7
@@
trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus {
qspi.rnode := pbus.toVariableWidthSlaves
qspi.fnode :=
TLFragmenter(1, pbus.blockBytes)(
qspi.rnode := pbus.toVariableWidthSlaves
qspi.fnode :=
TLFragmenter(1, pbus.blockBytes)(
- TLBuffer(BufferParams(
8
), BufferParams.none)(
+ TLBuffer(BufferParams(
params.fBufferDepth
), BufferParams.none)(
pbus.toFixedWidthSlaves))
ibus.fromSync := qspi.intnode
qspi
pbus.toFixedWidthSlaves))
ibus.fromSync := qspi.intnode
qspi