- val sample_d = ShiftRegisterInit(sample, c.sampleDelay, Bool(false))
- val last_d = ShiftRegisterInit(last, c.sampleDelay, Bool(false))
+ val sample_d = ShiftRegInit(sample, c.sampleDelay, init = Bool(false))
+ val last_d = ShiftRegInit(last, c.sampleDelay, init = Bool(false))