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devices: create periphery keys for all devices
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
spi
/
SPIPhysical.scala
diff --git
a/src/main/scala/devices/spi/SPIPhysical.scala
b/src/main/scala/devices/spi/SPIPhysical.scala
index cb26bc99046e3dbeb273b376e397b31c611b5567..802233da97db14f3509888de204da26a7446bd95 100644
(file)
--- a/
src/main/scala/devices/spi/SPIPhysical.scala
+++ b/
src/main/scala/devices/spi/SPIPhysical.scala
@@
-4,7
+4,7
@@
package sifive.blocks.devices.spi
import Chisel._
import sifive.blocks.util.ShiftRegisterInit
import Chisel._
import sifive.blocks.util.ShiftRegisterInit
-class SPIMicroOp(c: SPI
Config
Base) extends SPIBundle(c) {
+class SPIMicroOp(c: SPI
Params
Base) extends SPIBundle(c) {
val fn = Bits(width = 1)
val stb = Bool()
val cnt = UInt(width = c.countBits)
val fn = Bits(width = 1)
val stb = Bool()
val cnt = UInt(width = c.countBits)
@@
-16,12
+16,12
@@
object SPIMicroOp {
def Delay = UInt(1, 1)
}
def Delay = UInt(1, 1)
}
-class SPIPhyControl(c: SPI
Config
Base) extends SPIBundle(c) {
+class SPIPhyControl(c: SPI
Params
Base) extends SPIBundle(c) {
val sck = new SPIClocking(c)
val fmt = new SPIFormat(c)
}
val sck = new SPIClocking(c)
val fmt = new SPIFormat(c)
}
-class SPIPhysical(c: SPI
Config
Base) extends Module {
+class SPIPhysical(c: SPI
Params
Base) extends Module {
val io = new SPIBundle(c) {
val port = new SPIPortIO(c)
val ctrl = new SPIPhyControl(c).asInput
val io = new SPIBundle(c) {
val port = new SPIPortIO(c)
val ctrl = new SPIPhyControl(c).asInput