-class SPIGPIOPort(c: SPIParamsBase, syncStages: Int = 0, driveStrength: Bool = Bool(false)) extends Module {
- val io = new SPIBundle(c) {
- val spi = new SPIPortIO(c).flip
- val pins = new SPIPinsIO(c)
- }
+ val sck: T = pingen()
+ val dq: Vec[T] = Vec(4, pingen())
+ val cs: Vec[T] = Vec(c.csWidth, pingen())