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devices: create periphery keys for all devices
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
spi
/
SPIPins.scala
diff --git
a/src/main/scala/devices/spi/SPIPins.scala
b/src/main/scala/devices/spi/SPIPins.scala
index 48c302070c1fe0a882fa49b6b3e97f2aacd53fc9..cad5e0f3c8f6c18e3aeed683d57d61d1c8f1e160 100644
(file)
--- a/
src/main/scala/devices/spi/SPIPins.scala
+++ b/
src/main/scala/devices/spi/SPIPins.scala
@@
-4,13
+4,13
@@
package sifive.blocks.devices.spi
import Chisel._
import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
import Chisel._
import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
-class SPIPinsIO(c: SPI
Config
Base) extends SPIBundle(c) {
+class SPIPinsIO(c: SPI
Params
Base) extends SPIBundle(c) {
val sck = new GPIOPin
val dq = Vec(4, new GPIOPin)
val cs = Vec(c.csWidth, new GPIOPin)
}
val sck = new GPIOPin
val dq = Vec(4, new GPIOPin)
val cs = Vec(c.csWidth, new GPIOPin)
}
-class SPIGPIOPort(c: SPI
Config
Base, syncStages: Int = 0, driveStrength: Bool = Bool(false)) extends Module {
+class SPIGPIOPort(c: SPI
Params
Base, syncStages: Int = 0, driveStrength: Bool = Bool(false)) extends Module {
val io = new SPIBundle(c) {
val spi = new SPIPortIO(c).flip
val pins = new SPIPinsIO(c)
val io = new SPIBundle(c) {
val spi = new SPIPortIO(c).flip
val pins = new SPIPinsIO(c)