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Refactor package hierarchy.
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
spi
/
TLSPIFlash.scala
diff --git
a/src/main/scala/devices/spi/TLSPIFlash.scala
b/src/main/scala/devices/spi/TLSPIFlash.scala
index 8968c69bec666baa3c78d8ffce12c4242bd31fcf..1ded823a89b5d2427af9d041a85583f3d62566a9 100644
(file)
--- a/
src/main/scala/devices/spi/TLSPIFlash.scala
+++ b/
src/main/scala/devices/spi/TLSPIFlash.scala
@@
-2,10
+2,11
@@
package sifive.blocks.devices.spi
import Chisel._
package sifive.blocks.devices.spi
import Chisel._
-import config._
-import diplomacy._
-import regmapper._
-import uncore.tilelink2._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util.HeterogeneousBag
trait SPIFlashParamsBase extends SPIParamsBase {
val fAddress: BigInt
trait SPIFlashParamsBase extends SPIParamsBase {
val fAddress: BigInt
@@
-38,7
+39,7
@@
case class SPIFlashParams(
require(sampleDelay >= 0)
}
require(sampleDelay >= 0)
}
-class SPIFlashTopBundle(i:
util.HeterogeneousBag[Vec[Bool]], r: util.HeterogeneousBag[TLBundle], val f: util.
HeterogeneousBag[TLBundle]) extends SPITopBundle(i, r)
+class SPIFlashTopBundle(i:
HeterogeneousBag[Vec[Bool]], r: HeterogeneousBag[TLBundle], val f:
HeterogeneousBag[TLBundle]) extends SPITopBundle(i, r)
class SPIFlashTopModule[B <: SPIFlashTopBundle]
(c: SPIFlashParamsBase, bundle: => B, outer: TLSPIFlashBase)
class SPIFlashTopModule[B <: SPIFlashTopBundle]
(c: SPIFlashParamsBase, bundle: => B, outer: TLSPIFlashBase)