-trait HasPeripheryUARTBundle extends HasTopLevelNetworksBundle {
- val outer: HasPeripheryUART
- val uarts = Vec(outer.uartParams.size, new UARTPortIO)
+trait HasPeripheryUARTBundle {
+ val uarts: Vec[UARTPortIO]
+
+ def tieoffUARTs(dummy: Int = 1) {
+ uarts.foreach { _.rxd := UInt(1) }
+ }
+
+ def UARTtoGPIOPins(syncStages: Int = 0): Seq[UARTPinsIO] = uarts.map { u =>
+ val pin = Module(new UARTGPIOPort(syncStages))
+ pin.io.uart <> u
+ pin.io.pins
+ }