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uart: use PeripheryBusKey (#38)
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
uart
/
UARTPeriphery.scala
diff --git
a/src/main/scala/devices/uart/UARTPeriphery.scala
b/src/main/scala/devices/uart/UARTPeriphery.scala
index cb79845e4879f811dceda48ae6f1a3112537c69a..de4392c8860ed9d2e07f40dea243fbb91ccb9a83 100644
(file)
--- a/
src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/
src/main/scala/devices/uart/UARTPeriphery.scala
@@
-4,18
+4,18
@@
package sifive.blocks.devices.uart
import Chisel._
import chisel3.experimental.{withClockAndReset}
import freechips.rocketchip.config.Field
import Chisel._
import chisel3.experimental.{withClockAndReset}
import freechips.rocketchip.config.Field
-import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus}
+import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
+import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus}
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import sifive.blocks.devices.pinctrl.{Pin}
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import sifive.blocks.devices.pinctrl.{Pin}
-import sifive.blocks.util.ShiftRegisterInit
case object PeripheryUARTKey extends Field[Seq[UARTParams]]
trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
case object PeripheryUARTKey extends Field[Seq[UARTParams]]
trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
- val uartParams = p(PeripheryUARTKey)
- val
divinit = (p(PeripheryBusParams).frequency / 115200).toInt
+ private val divinit = (p(PeripheryBusKey).frequency / 115200).toInt
+ val
uartParams = p(PeripheryUARTKey).map(_.copy(divisorInit = divinit))
val uarts = uartParams map { params =>
val uarts = uartParams map { params =>
- val uart = LazyModule(new TLUART(pbus.beatBytes, params
.copy(divisorInit = divinit)
))
+ val uart = LazyModule(new TLUART(pbus.beatBytes, params))
uart.node := pbus.toVariableWidthSlaves
ibus.fromSync := uart.intnode
uart
uart.node := pbus.toVariableWidthSlaves
ibus.fromSync := uart.intnode
uart
@@
-51,7
+51,7
@@
class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
withClockAndReset(clock, reset) {
txd.outputPin(uart.txd)
val rxd_t = rxd.inputPin()
withClockAndReset(clock, reset) {
txd.outputPin(uart.txd)
val rxd_t = rxd.inputPin()
- uart.rxd := S
hiftRegisterInit(rxd_t, syncStages, Bool(true
))
+ uart.rxd := S
yncResetSynchronizerShiftReg(rxd_t, syncStages, init = Bool(true), name = Some("uart_rxd_sync"
))
}
}
}
}
}
}