import chisel3.experimental.{withClockAndReset}
import freechips.rocketchip.config.Field
import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
import chisel3.experimental.{withClockAndReset}
import freechips.rocketchip.config.Field
import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import sifive.blocks.devices.pinctrl.{Pin}
case object PeripheryUARTKey extends Field[Seq[UARTParams]]
trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import sifive.blocks.devices.pinctrl.{Pin}
case object PeripheryUARTKey extends Field[Seq[UARTParams]]
trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
val uartParams = p(PeripheryUARTKey).map(_.copy(divisorInit = divinit))
val uarts = uartParams map { params =>
val uart = LazyModule(new TLUART(pbus.beatBytes, params))
val uartParams = p(PeripheryUARTKey).map(_.copy(divisorInit = divinit))
val uarts = uartParams map { params =>
val uart = LazyModule(new TLUART(pbus.beatBytes, params))