- def fromUARTPort(uart: UARTPortIO, syncStages: Int = 0) {
- txd.outputPin(uart.txd)
- val rxd_t = rxd.inputPin()
- uart.rxd := ShiftRegisterInit(rxd_t, syncStages, Bool(true))
+ override def cloneType: this.type =
+ this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
+
+ def fromPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
+ withClockAndReset(clock, reset) {
+ txd.outputPin(uart.txd)
+ val rxd_t = rxd.inputPin()
+ uart.rxd := SyncResetSynchronizerShiftReg(rxd_t, syncStages, init = Bool(true), name = Some("uart_rxd_sync"))
+ }