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u500vc707devkit 4GB : new address map allows switch to paramterization with address...
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
xilinxvc707mig
/
XilinxVC707MIGPeriphery.scala
diff --git
a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
index 59dd4a0df967cb58e54c7c11c048fe2e89d0a892..7aebfae7c30cf9f9162e2b0f7b34831ad35e5e69 100644
(file)
--- a/
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
+++ b/
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
@@
-4,7
+4,7
@@
package sifive.blocks.devices.xilinxvc707mig
import Chisel._
import freechips.rocketchip.config._
import freechips.rocketchip.coreplex.HasMemoryBus
import Chisel._
import freechips.rocketchip.config._
import freechips.rocketchip.coreplex.HasMemoryBus
-import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp
, AddressRange
}
case object MemoryXilinxDDRKey extends Field[XilinxVC707MIGParams]
case object MemoryXilinxDDRKey extends Field[XilinxVC707MIGParams]
@@
-27,7
+27,10
@@
trait HasMemoryXilinxVC707MIGBundle {
trait HasMemoryXilinxVC707MIGModuleImp extends LazyMultiIOModuleImp
with HasMemoryXilinxVC707MIGBundle {
val outer: HasMemoryXilinxVC707MIG
trait HasMemoryXilinxVC707MIGModuleImp extends LazyMultiIOModuleImp
with HasMemoryXilinxVC707MIGBundle {
val outer: HasMemoryXilinxVC707MIG
- val xilinxvc707mig = IO(new XilinxVC707MIGIO(p(MemoryXilinxDDRKey).depthGB))
+ val ranges = AddressRange.fromSets(p(MemoryXilinxDDRKey).address)
+ require (ranges.size == 1, "DDR range must be contiguous")
+ val depth = ranges.head.size
+ val xilinxvc707mig = IO(new XilinxVC707MIGIO(depth))
xilinxvc707mig <> outer.xilinxvc707mig.module.io.port
}
xilinxvc707mig <> outer.xilinxvc707mig.module.io.port
}