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vc707 axi enhancements (#24)
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
xilinxvc707pciex1
/
XilinxVC707PCIeX1.scala
diff --git
a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
index 9bb0c05ddd052296c786b71c95a3aa660f387020..76239cfc8dbf41c5543cf98c211f81749669ada0 100644
(file)
--- a/
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
+++ b/
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
@@
-32,13
+32,13
@@
class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
AXI4UserYanker()(
AXI4Deinterleaver(p(coreplex.CacheBlockBytes))(
AXI4IdIndexer(idBits=4)(
AXI4UserYanker()(
AXI4Deinterleaver(p(coreplex.CacheBlockBytes))(
AXI4IdIndexer(idBits=4)(
- TLToAXI4(beatBytes=8)(
+ TLToAXI4(beatBytes=8
, adapterName = Some("pcie-slave")
)(
TLAsyncCrossingSink()(
slave))))))
axi_to_pcie_x1.control :=
AXI4Buffer()(
TLAsyncCrossingSink()(
slave))))))
axi_to_pcie_x1.control :=
AXI4Buffer()(
- AXI4UserYanker()(
+ AXI4UserYanker(
capMaxFlight = Some(2)
)(
TLToAXI4(beatBytes=4)(
TLFragmenter(4, p(coreplex.CacheBlockBytes))(
TLAsyncCrossingSink()(
TLToAXI4(beatBytes=4)(
TLFragmenter(4, p(coreplex.CacheBlockBytes))(
TLAsyncCrossingSink()(