-trait PeripheryXilinxVC707PCIeX1Module extends TopNetworkModule {
- val outer: PeripheryXilinxVC707PCIeX1
- val io: PeripheryXilinxVC707PCIeX1Bundle
+trait HasSystemXilinxVC707PCIeX1ModuleImp extends LazyMultiIOModuleImp
+ with HasSystemXilinxVC707PCIeX1Bundle {
+ val outer: HasSystemXilinxVC707PCIeX1
+ val xilinxvc707pcie = IO(new XilinxVC707PCIeX1IO)
+
+ xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port