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uart: make it easy to simulate large text printouts (#33)
[sifive-blocks.git]
/
src
/
main
/
scala
/
ip
/
xilinx
/
vc707axi_to_pcie_x1
/
vc707axi_to_pcie_x1.scala
diff --git
a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
index c7206e41e78666c8fa98c2f533cf85081ba0527e..7e732f8160e5dfa6823f71cd4442756ad1240792 100644
(file)
--- a/
src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
+++ b/
src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
@@
-2,11
+2,10
@@
package sifive.blocks.ip.xilinx.vc707axi_to_pcie_x1
import Chisel._
package sifive.blocks.ip.xilinx.vc707axi_to_pcie_x1
import Chisel._
-import config._
-import diplomacy._
-import uncore.axi4._
-import uncore.tilelink2.{IntSourceNode, IntSourcePortSimple}
-import junctions._
+import freechips.rocketchip.config._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.amba.axi4._
+import freechips.rocketchip.tilelink.{IntSourceNode, IntSourcePortSimple}
// IP VLNV: xilinx.com:customize_ip:vc707pcietoaxi:1.0
// Black Box
// IP VLNV: xilinx.com:customize_ip:vc707pcietoaxi:1.0
// Black Box