- val io = new Bundle with VC707MIGUnidirectionalIODDR
- with VC707MIGUnidirectionalIOClocksReset {
- // bidirectional signals on blackbox interface
- // defined here as an output so "__inout" signal name does not have to be used
- // verilog does not check the
- val ddr3_dq = Bits(OUTPUT,64)
- val ddr3_dqs_n = Bits(OUTPUT,8)
- val ddr3_dqs_p = Bits(OUTPUT,8)