from nmigen.compat.sim import run_simulation
from nmigen.cli import verilog, rtlil
from nmigen.compat.sim import run_simulation
from nmigen.cli import verilog, rtlil
-from nmigen import Record, Signal, Module, Const, Elaboratable
+from nmigen import Record, Signal, Module, Const, Elaboratable, Mux
def latchregister(m, incoming, outgoing, settrue, name=None):
"""latchregister
def latchregister(m, incoming, outgoing, settrue, name=None):
"""latchregister
reg = Record.like(incoming, name=name)
else:
reg = Signal.like(incoming, name=name)
reg = Record.like(incoming, name=name)
else:
reg = Signal.like(incoming, name=name)
def mkname(prefix, suffix):
if suffix is None:
return prefix
return "%s_%s" % (prefix, suffix)
def mkname(prefix, suffix):
if suffix is None:
return prefix
return "%s_%s" % (prefix, suffix)
class SRLatch(Elaboratable):
def __init__(self, sync=True, llen=1, name=None):
self.sync = sync
self.llen = llen
s_n, r_n = mkname("s", name), mkname("r", name)
q_n, qn_n = mkname("q", name), mkname("qn", name)
class SRLatch(Elaboratable):
def __init__(self, sync=True, llen=1, name=None):
self.sync = sync
self.llen = llen
s_n, r_n = mkname("s", name), mkname("r", name)
q_n, qn_n = mkname("q", name), mkname("qn", name)
qlq_n = mkname("qlq", name)
self.s = Signal(llen, name=s_n, reset=0)
qlq_n = mkname("qlq", name)
self.s = Signal(llen, name=s_n, reset=0)
self.q = Signal(llen, name=q_n, reset_less=True)
self.qn = Signal(llen, name=qn_n, reset_less=True)
self.qlq = Signal(llen, name=qlq_n, reset_less=True)
self.q = Signal(llen, name=q_n, reset_less=True)
self.qn = Signal(llen, name=qn_n, reset_less=True)
self.qlq = Signal(llen, name=qlq_n, reset_less=True)
- m.d.sync += q_int.eq((q_int & ~self.r) | self.s)
+ next_o = Signal(self.llen, reset_less=True)
+ m.d.comb += next_o.eq((self.q_int & ~self.r) | self.s)
+ m.d.sync += self.q_int.eq(next_o)