- reg = Signal.like(incoming, name=name) # make reg same as input. reset OK.
- with m.If(settrue): # pass in some kind of expression/condition here
+ """latchregister
+
+ based on a conditon, "settrue", incoming data will be "latched"
+ into a register and passed out on "outgoing".
+
+ * if "settrue" is ASSERTED, outgoing is COMBINATORIALLY equal to incoming
+ * on the same cycle that settrue is DEASSERTED, outgoing REMAINS
+ equal (indefinitely) to the incoming value
+ """
+ # make reg same as input. reset OK.
+ if isinstance(incoming, Record):
+ reg = Record.like(incoming, name=name)
+ else:
+ reg = Signal.like(incoming, name=name)
+ m.d.comb += outgoing.eq(Mux(settrue, incoming, reg))
+ with m.If(settrue): # pass in some kind of expression/condition here