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rename sd to mmc to avoid name clash with sdram
[pinmux.git]
/
src
/
spec
/
pinfunctions.py
diff --git
a/src/spec/pinfunctions.py
b/src/spec/pinfunctions.py
index 0aa4ae8ba8f79e454798f5c0d9f61ba6be2e62b4..80a51296d6b9e18d8490b4330532c50882921dec 100644
(file)
--- a/
src/spec/pinfunctions.py
+++ b/
src/spec/pinfunctions.py
@@
-73,6
+73,7
@@
def nspi(suffix, bank, iosize, masteronly=True):
inout.append(pname)
return (qpins, inout)
inout.append(pname)
return (qpins, inout)
+
def mspi(suffix, bank):
return nspi(suffix, bank, 2, masteronly=True)
def mspi(suffix, bank):
return nspi(suffix, bank, 2, masteronly=True)
@@
-94,7
+95,7
@@
def i2c(suffix, bank):
def jtag(suffix, bank):
def jtag(suffix, bank):
- return (['TMS
+
', 'TDI-', 'TDO+', 'TCK+'], [])
+ return (['TMS
-
', 'TDI-', 'TDO+', 'TCK+'], [])
def uart(suffix, bank):
def uart(suffix, bank):
@@
-142,11
+143,12
@@
def flexbus1(suffix, bank):
inout.append(pname)
for i in range(2):
buspins.append("CS%d+" % i)
inout.append(pname)
for i in range(2):
buspins.append("CS%d+" % i)
- buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK+',
- 'A0', 'A1', 'TS', 'TBST',
- 'TSIZ0', 'TSIZ1']
+ buspins += ['ALE+', 'OE+', 'RW+', 'TA-',
+ # 'TS+', commented out for now, mirrors ALE, for mux'd mode
+ 'TBST+',
+ 'TSIZ0+', 'TSIZ1+']
for i in range(4):
for i in range(4):
- buspins.append("BWE%d" % i)
+ buspins.append("BWE%d
+
" % i)
for i in range(2, 6):
buspins.append("CS%d+" % i)
return (buspins, inout)
for i in range(2, 6):
buspins.append("CS%d+" % i)
return (buspins, inout)
@@
-162,33
+164,45
@@
def flexbus2(suffix, bank):
def sdram1(suffix, bank):
buspins = []
inout = []
def sdram1(suffix, bank):
buspins = []
inout = []
- for i in range(16):
- pname = "SDRDQM%d*" % i
+ for i in range(8):
+ pname = "SDRDQM%d+" % i
+ buspins.append(pname)
+ for i in range(8):
+ pname = "SDRD%d*" % i
buspins.append(pname)
inout.append(pname)
for i in range(12):
buspins.append("SDRAD%d+" % i)
buspins.append(pname)
inout.append(pname)
for i in range(12):
buspins.append("SDRAD%d+" % i)
- for i in range(8):
- buspins.append("SDRDQ%d+" % i)
- for i in range(3):
- buspins.append("SDRCS%d#+" % i)
- for i in range(2):
- buspins.append("SDRDQ%d+" % i)
for i in range(2):
buspins.append("SDRBA%d+" % i)
for i in range(2):
buspins.append("SDRBA%d+" % i)
- buspins += ['SDRCKE+', 'SDRRAS
#+', 'SDRCAS#+', 'SDRWE#
+',
- 'SDR
RST
+']
+ buspins += ['SDRCKE+', 'SDRRAS
n+', 'SDRCASn+', 'SDRWEn
+',
+ 'SDR
CSn0
+']
return (buspins, inout)
def sdram2(suffix, bank):
buspins = []
inout = []
return (buspins, inout)
def sdram2(suffix, bank):
buspins = []
inout = []
- for i in range(
3
, 6):
- buspins.append("SDRCS
%d#
+" % i)
- for i in range(
16, 32
):
+ for i in range(
1
, 6):
+ buspins.append("SDRCS
n%d
+" % i)
+ for i in range(
8, 16
):
pname = "SDRDQM%d*" % i
buspins.append(pname)
pname = "SDRDQM%d*" % i
buspins.append(pname)
+ for i in range(8, 16):
+ pname = "SDRD%d*" % i
+ buspins.append(pname)
+ inout.append(pname)
+ return (buspins, inout)
+
+
+def sdram3(suffix, bank):
+ buspins = []
+ inout = []
+ for i in range(12, 13):
+ buspins.append("SDRAD%d+" % i)
+ for i in range(8, 64):
+ pname = "SDRD%d*" % i
+ buspins.append(pname)
inout.append(pname)
return (buspins, inout)
inout.append(pname)
return (buspins, inout)
@@
-238,8
+252,8
@@
def gpio(suffix, bank):
# list functions by name here
pinspec = (('IIS', i2s),
# list functions by name here
pinspec = (('IIS', i2s),
- ('MMC', emmc),
- ('
SD
', sdmmc),
+ ('
E
MMC', emmc),
+ ('
MMC
', sdmmc),
('MSPI', mspi),
('MQSPI', mquadspi),
('SPI', spi),
('MSPI', mspi),
('MQSPI', mquadspi),
('SPI', spi),
@@
-255,6
+269,7
@@
pinspec = (('IIS', i2s),
('FB', flexbus2),
('SDR', sdram1),
('SDR', sdram2),
('FB', flexbus2),
('SDR', sdram1),
('SDR', sdram2),
+ ('SDR', sdram3),
('EINT', eint),
('PWM', pwm),
('GPIO', gpio),
('EINT', eint),
('PWM', pwm),
('GPIO', gpio),