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moved CLK away from testout
[pinmux.git]
/
src
/
spec
/
pinfunctions.py
diff --git
a/src/spec/pinfunctions.py
b/src/spec/pinfunctions.py
index f5f61d76c7410ac3045f5f332319ddde3bacbdc0..f921f2b4a6f8c7c0ef59616c4db7a770089780f7 100644
(file)
--- a/
src/spec/pinfunctions.py
+++ b/
src/spec/pinfunctions.py
@@
-286,8
+286,8
@@
def vdd(suffix, bank):
def sys(suffix, bank):
return (['RST-', # reset line
def sys(suffix, bank):
return (['RST-', # reset line
+ 'PLLCLK-', # incoming clock (to PLL)
'PLLSELA0-', 'PLLSELA1-', # PLL divider-selector
'PLLSELA0-', 'PLLSELA1-', # PLL divider-selector
- 'PLLCLK-', # incoming clock (to PLL)
'PLLTESTOUT+', # divided-output (for testing)
'PLLVCOUT+', # PLL VCO analog out (for testing)
], [], 'CLK')
'PLLTESTOUT+', # divided-output (for testing)
'PLLVCOUT+', # PLL VCO analog out (for testing)
], [], 'CLK')