soc/integration/csr_bridge: use registered version only when SDRAM is present.

[litex.git] / CHANGES

diff --git a/CHANGES b/CHANGES
index f4b28cd8ad9f1544ccbe6af470d503ae30637a1b..836fead16a5851756323be19f78abe660beec87f 100644 (file)
--- a/CHANGES
+++ b/CHANGES
@@ -4,18 +4,40 @@
        [> Issues resolved
        ------------------
        - Fix flush_cpu_icache on VexRiscv.
+       - Fix `.data` section placed in rom (#566)
 
        [> Added Features
        ------------------
-       - BIOS history, autocomplete.
-       - Pluggable CPUs.
-       - Add nMigen dependency.
        - Properly integrate Minerva CPU.
+       - Add nMigen dependency.
+       - Pluggable CPUs.
+       - BIOS history, autocomplete.
+       - Improve boards's programmers.
+       - Add Microwatt CPU support (with GHDL-Yosys-plugin support for FOSS toolchains).
+       - Speedup Memtest using an LFSR.
+       - Add LedChaser on boards.
+       - Improve WishboneBridge.
+       - Improve Diamond constraints.
+       - Use InterconnectPointToPoint when 1 master,1 slave and no address translation.
+       - Add CV32E40P CPU support (ex RI5CY).
+       - JTAG UART with uart_name=jtag_uart (validated on Spartan6, 7-Series, Ultrascale(+)).
+       - Add Symbiflow experimental support on Arty.
+       - Add SDCard (SPI and SD modes) boot from FAT/exFAT filesystems with FatFs.
+       - Simplify boot with boot.json configuration file.
+       - Revert to a single crt0 (avoid ctr/xip variants).
+       - Add otional DMA bus for Cache Coherency on CPU(s) with DMA/Cache Coherency interface.
+       - Add AXI-Lite bus standard support.
+       - Add VexRiscv SMP CPU support.
 
        [> API changes/Deprecation
        --------------------------
-       - NA
-
+       - Add --build --load arguments to targets.
+       - Deprecate soc.interconnect.wishbone.UpConverter (will be rewritten if useful).
+       - Deprecate soc.interconnect.wishbone.CSRBank (Does not seem to be used by anyone).
+       - Move soc.interconnect.wishbone2csr.WB2CSR to soc.interconnect.wishbone.Wishbone2CSR.
+       - Move soc.interconnect.wishbonebridge.WishboneStreamingBridge to soc.cores.uart.Stream2Wishbone.
+       - Rename --gateware-toolchain target parameter to --toolchain.
+       - Integrate Zynq's PS7 as a regular CPU (zynq7000) and deprecate SoCZynq.
 
 [> 2020.04, released April 28th, 2020
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