litedram/generated/rcs-arctic-tern-bmc-card/litedram-initmem.vhdl
soc_extra_v += litedram/generated/rcs-arctic-tern-bmc-card/litedram_core.v
soc_extra_v += liteeth/generated/rcs-arctic-tern-bmc-card/liteeth_core.v
+soc_extra_v += tercel/phy.v
+soc_extra_v += tercel/wishbone_spi_master.v
endif
GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \