Other nMigen libraries are built on FHDL and provide various tools and logic cores. nMigen also contains a simulator that allows test benches to be written in Python.
-See the [doc/](doc/) folder for more technical information.
+nMigen is based on Migen, a similar Python-based hardware description language. Although Migen works very well in production, its design could be improved in many fundamental ways, and nMigen reimplements Migen concepts from scratch to do so. nMigen also provides an extensive [compatibility layer](#migration-from-migen) that makes it possible to build and simulate most Migen designs unmodified, as well as integrate modules written for Migen and nMigen.
-nMigen is a direct descendant of [Migen][] rewritten from scratch to address many issues that became clear in the many years Migen has been used in production. nMigen provides an extensive [compatibility layer](#migration-from-migen) that makes it possible to build and simulate most Migen designs unmodified, as well as integrate modules written for Migen and nMigen.
+The development of nMigen has been supported by [SymbioticEDA][], [LambdaConcept][], and [ChipEleven][].
-nMigen is designed for Python 3.6 and newer. nMigen's Verilog backend requires [Yosys][] 0.9 or a newer version.
-
-Thanks [LambdaConcept][] for being a sponsor of this project! Contact sb [at] m-labs.hk if you also wish to support this work.
-
-[migen]: https://m-labs.hk/migen
[yosys]: http://www.clifford.at/yosys/
+[symbioticeda]: https://www.symbioticeda.com/
[lambdaconcept]: http://lambdaconcept.com/
+[chipeleven]: https://chipeleven.com/
-### HLS?
+### Introduction
-nMigen is *not* a "Python-to-FPGA" conventional high level synthesis (HLS) tool. It will *not* take a Python program as input and generate a hardware implementation of it. In nMigen, the Python program is executed by a regular Python interpreter, and it emits explicit statements in the FHDL domain-specific language. Writing a conventional HLS tool that uses nMigen as an internal component might be a good idea, on the other hand :)
+See the [Introduction](https://nmigen.info/nmigen/latest/intro.html) section of the documentation.
### Installation
-nMigen requires [Yosys][] 0.9 or newer, as well as a device-specific toolchain.
+See the [Installation](https://nmigen.info/nmigen/latest/install.html) section of the documentation.
- pip install git+https://github.com/m-labs/nmigen.git
- pip install git+https://github.com/m-labs/nmigen-boards.git
+### Supported devices
-### Introduction
+nMigen can be used to target any FPGA or ASIC process that accepts behavioral Verilog-2001 as input. It also offers extended support for many FPGA families, providing toolchain integration, abstractions for device-specific primitives, and more. Specifically:
-TBD
+ * Lattice iCE40 (toolchains: **Yosys+nextpnr**, LSE-iCECube2, Synplify-iCECube2);
+ * Lattice MachXO2 (toolchains: Diamond);
+ * Lattice MachXO3L (toolchains: Diamond);
+ * Lattice ECP5 (toolchains: **Yosys+nextpnr**, Diamond);
+ * Xilinx Spartan 3A (toolchains: ISE);
+ * Xilinx Spartan 6 (toolchains: ISE);
+ * Xilinx 7-series (toolchains: Vivado);
+ * Xilinx UltraScale (toolchains: Vivado);
+ * Intel (toolchains: Quartus);
+ * Quicklogic EOS S3 (toolchains: **Yosys+VPR**).
-### Migration from [Migen][]
+FOSS toolchains are listed in **bold**.
-If you are already familiar with [Migen][], the good news is that nMigen provides a comprehensive Migen compatibility layer! An existing Migen design can be synthesized and simulated with nMigen in three steps:
+### Migration from Migen
+
+If you are already familiar with Migen, the good news is that nMigen provides a comprehensive Migen compatibility layer! An existing Migen design can be synthesized and simulated with nMigen in three steps:
1. Replace all `from migen import <...>` statements with `from nmigen.compat import <...>`.
2. Replace every explicit mention of the default `sys` clock domain with the new default `sync` clock domain. E.g. `ClockSignal("sys")` is changed to `ClockSignal("sync")`.
Once your design passes verification with nMigen, you can migrate it to the nMigen syntax one module at a time. Migen modules can be added to nMigen modules and vice versa, so there is no restriction on the order of migration, either.
-### License
-
-nMigen is released under the very permissive two-clause BSD license. Under the terms of this license, you are authorized to use nMigen for closed-source proprietary designs.
+### Community
-Even though we do not require you to do so, these things are awesome, so please do them if possible:
- * tell us that you are using nMigen
- * put the [nMigen logo](doc/nmigen_logo.svg) on the page of a product using it, with a link to https://m-labs.hk
- * cite nMigen in publications related to research it has helped
- * send us feedback and suggestions for improvements
- * send us bug reports when something goes wrong
- * send us the modifications and improvements you have done to nMigen as pull requests on GitHub
+nMigen has a dedicated IRC channel, [#nmigen at freenode.net](https://webchat.freenode.net/?channels=nmigen). Feel free to join to ask questions about using nMigen or discuss ongoing development of nMigen and its related projects.
-See LICENSE file for full copyright and license info.
+### License
- "Electricity! It's like magic!"
+nMigen is released under the very permissive [two-clause BSD license](LICENSE.txt). Under the terms of this license, you are authorized to use nMigen for closed-source proprietary designs.
projects / nmigen.git / blobdiff