Use new toolchain and calling convention

[riscv-tests.git] / benchmarks / common / crt.S

diff --git a/benchmarks/common/crt.S b/benchmarks/common/crt.S
index 82cad93f76e8d4292a935587ab6122b6a0e1dd38..24d22e8e6f09d0c9db1bb55c5410299bc9dcaa43 100644 (file)
--- a/benchmarks/common/crt.S
+++ b/benchmarks/common/crt.S
@@ -44,21 +44,20 @@ _start:
   li  x30,0
   li  x31,0
 
+  # initialize status, enable fp, accelerator, interrupts
+  li a0, SR_S | SR_PEI | SR_EF | SR_EA
+  csrw status, a0
+
 #ifdef __riscv64
   li a0, SR_U64 | SR_S64
   csrs status, a0
 #endif
-  csrc status, SR_PS
-
-  # enable fp and accelerator
-  li a0, SR_EF | SR_EA
-  csrs status, a0
 
   csrr t0, status
   and t1, t0, SR_EA
   sw t1, have_vec, t2
 
-  ## if that didn't stick, we don't have an FPU, so don't initialize it
+  ## if that didn't stick, we don't have a FPU, so don't initialize it
   and t1, t0, SR_EF
   beqz t1, 1f
 
@@ -115,8 +114,11 @@ _start:
   sll sp, sp, STKSHIFT
   add sp, sp, tp
 
+  # offset thread pointer by thread pointer bias
   lui t0, %tprel_hi(tls_start)
+  add t0, t0, tp, %tprel_add(tls_start)
   add t0, t0, %tprel_lo(tls_start)
+  sub t0, t0, tp
   sub tp, tp, t0
 
   la t0, _init
@@ -175,7 +177,7 @@ trap_entry:
   csrr a1, epc
   mv a2, sp
   jal handle_trap
-  csrw epc, v0
+  csrw epc, a0
 
   LREG t0, 256(sp)
   LREG t1, 264(sp)