uint32_t dword;
puts("gram_read: ");
- uart_writeuint32(addr);
- dword = readl(addr);
+ uart_writeuint32((unsigned long)addr);
+ dword = readl((unsigned long)addr);
puts(": ");
- uart_writeuint32(dword);
+ uart_writeuint32((unsigned long)dword);
puts("\n");
return dword;
int gram_write(const struct gramCtx *ctx, void *addr, uint32_t value) {
puts("gram_write: ");
- uart_writeuint32(addr);
+ uart_writeuint32((unsigned long)addr);
puts(": ");
- uart_writeuint32(value);
- writel(value, addr);
+ uart_writeuint32((unsigned long)value);
+ writel(value, (unsigned long)addr);
puts("\n");
return 0;
int main(void) {
const int kNumIterations = 14;
- int res, failcnt = 0, i=0;
+ int res, failcnt = 0;
uint32_t tmp;
+ unsigned long ftr, val;
volatile uint32_t *ram = (uint32_t*)DRAM_BASE;
console_init();
//puts("Firmware launched...\n");
- puts("fw..");
+#if 1
+ puts(" Soc signature: ");
+ tmp = readl(SYSCON_BASE + SYS_REG_SIGNATURE);
+ uart_writeuint32(tmp);
+ puts(" Soc features: ");
+ ftr = readl(SYSCON_BASE + SYS_REG_INFO);
+ if (ftr & SYS_REG_INFO_HAS_UART)
+ puts("UART ");
+ if (ftr & SYS_REG_INFO_HAS_DRAM)
+ puts("DRAM ");
+ if (ftr & SYS_REG_INFO_HAS_BRAM)
+ puts("BRAM ");
+ if (ftr & SYS_REG_INFO_HAS_SPI_FLASH)
+ puts("SPIFLASH ");
+ if (ftr & SYS_REG_INFO_HAS_LITEETH)
+ puts("ETHERNET ");
+ puts("\r\n");
+
+ if (ftr & SYS_REG_INFO_HAS_SPI_FLASH) {
+ puts("SPI Offset: ");
+ val = readl(SYSCON_BASE + SYS_REG_SPI_INFO);
+ uart_writeuint32(val);
+ puts("\r\n");
+ }
+
+#endif
+
#if 0
#if 1
// print out configuration parameters for QSPI