Remove verilog header files built from Chisel .prm file.

[freedom-sifive.git] / common.mk

diff --git a/common.mk b/common.mk
index e09cc29a1483485a241437d929269f8dfcf2a3f9..74f74de59c40891b8f4ea9af77366e8cfc772363 100644 (file)
--- a/common.mk
+++ b/common.mk
@@ -47,20 +47,13 @@ ifneq ($(PATCHVERILOG),"")
 endif
 
 
-verilog_consts_vh := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).vh
-$(verilog_consts_vh): $(firrtl_prm)
-       echo "\`ifndef CONST_VH" > $@
-       echo "\`define CONST_VH" >> $@
-       sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $< >> $@
-       echo "\`endif // CONST_VH" >> $@
-
 .PHONY: verilog
-verilog: $(verilog) $(verilog_consts_vh)
+verilog: $(verilog)
 
 # Build .mcs
 mcs := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).mcs
-$(mcs): $(verilog) $(verilog_consts_vh)
-       VSRC_TOP=$(verilog) VSRC_CONSTS=$(verilog_consts_vh) EXTRA_VSRCS="$(EXTRA_FPGA_VSRCS)" $(MAKE) -C $(FPGA_DIR) mcs
+$(mcs): $(verilog)
+       VSRC_TOP=$(verilog) EXTRA_VSRCS="$(EXTRA_FPGA_VSRCS)" $(MAKE) -C $(FPGA_DIR) mcs
        cp $(FPGA_DIR)/obj/system.mcs $@
 
 .PHONY: mcs