Add Tercel PHY reset synchronization

[microwatt.git] / core_dram_tb.vhdl

diff --git a/core_dram_tb.vhdl b/core_dram_tb.vhdl
index d0890cba87bcbb3c0b6b23e4bfac6aad4a651f17..f65125a43670394a8e5ac7fca52d48153760e23e 100644 (file)
--- a/core_dram_tb.vhdl
+++ b/core_dram_tb.vhdl
@@ -120,6 +120,9 @@ begin
         generic map(
             DRAM_ABITS => 24,
             DRAM_ALINES => 1,
+            DRAM_DLINES => 16,
+            DRAM_CKLINES => 1,
+            DRAM_PORT_WIDTH => 128,
             PAYLOAD_FILE => DRAM_INIT_FILE,
             PAYLOAD_SIZE => ROM_SIZE
             )