Add Tercel PHY reset synchronization

[microwatt.git] / core_tb.vhdl

diff --git a/core_tb.vhdl b/core_tb.vhdl
index 1c463d7f9588e7fd5b49ae4f8d65f3ce89c2958c..162c93fa439d4375507c57234e8906e2317394a2 100644 (file)
--- a/core_tb.vhdl
+++ b/core_tb.vhdl
@@ -1,5 +1,6 @@
 library ieee;
 use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
 
 library work;
 use work.common.all;
@@ -11,47 +12,38 @@ end core_tb;
 architecture behave of core_tb is
        signal clk, rst: std_logic;
 
-       signal wishbone_in : wishbone_slave_out;
-       signal wishbone_out : wishbone_master_out;
-
-       signal registers : regfile;
-       signal terminate : std_ulogic;
-
        -- testbench signals
        constant clk_period : time := 10 ns;
 begin
-       core_0: entity work.core
-               generic map (SIM => true)
-               port map (clk => clk, rst => rst, wishbone_in => wishbone_in,
-                         wishbone_out => wishbone_out, registers => registers, terminate_out => terminate);
-
-       simple_ram_0: entity work.simple_ram_behavioural
-               generic map ( filename => "simple_ram_behavioural.bin", size => 1048576)
-               port map (clk => clk, rst => rst, wishbone_in => wishbone_out, wishbone_out => wishbone_in);
-
-       clk_process: process
-       begin
-               clk <= '0';
-               wait for clk_period/2;
-               clk <= '1';
-               wait for clk_period/2;
-       end process;
-
-       rst_process: process
-       begin
-               rst <= '1';
-               wait for 10*clk_period;
-               rst <= '0';
-               wait;
-       end process;
-
-       dump_registers: process(all)
-       begin
-               if terminate = '1' then
-                       loop_0: for i in 0 to 31 loop
-                               report "REG " & to_hstring(registers(i));
-                       end loop loop_0;
-                       assert false report "end of test" severity failure;
-               end if;
-       end process;
+
+    soc0: entity work.soc
+       generic map(
+           SIM => true,
+           MEMORY_SIZE => (384*1024),
+           RAM_INIT_FILE => "main_ram.bin",
+           CLK_FREQ => 100000000
+           )
+       port map(
+           rst => rst,
+           system_clk => clk
+           );
+
+    clk_process: process
+    begin
+       clk <= '0';
+       wait for clk_period/2;
+       clk <= '1';
+       wait for clk_period/2;
+    end process;
+
+    rst_process: process
+    begin
+       rst <= '1';
+       wait for 10*clk_period;
+       rst <= '0';
+       wait;
+    end process;
+
+    jtag: entity work.sim_jtag;
+
 end;