Add Tercel PHY reset synchronization

[microwatt.git] / core_tb.vhdl

diff --git a/core_tb.vhdl b/core_tb.vhdl
index 672b4246b342b5f786689037075be452cdd61d1f..162c93fa439d4375507c57234e8906e2317394a2 100644 (file)
--- a/core_tb.vhdl
+++ b/core_tb.vhdl
@@ -19,15 +19,13 @@ begin
     soc0: entity work.soc
        generic map(
            SIM => true,
-           MEMORY_SIZE => 524288,
-           RAM_INIT_FILE => "simple_ram_behavioural.bin",
-           RESET_LOW => false
+           MEMORY_SIZE => (384*1024),
+           RAM_INIT_FILE => "main_ram.bin",
+           CLK_FREQ => 100000000
            )
        port map(
            rst => rst,
-           system_clk => clk,
-           uart0_rxd => '0',
-           uart0_txd => open
+           system_clk => clk
            );
 
     clk_process: process
@@ -47,4 +45,5 @@ begin
     end process;
 
     jtag: entity work.sim_jtag;
+
 end;