Add Tercel PHY reset synchronization

[microwatt.git] / core_tb.vhdl

diff --git a/core_tb.vhdl b/core_tb.vhdl
index a35d73d54ab864aafc14bb8b25acdcf773ab9db1..162c93fa439d4375507c57234e8906e2317394a2 100644 (file)
--- a/core_tb.vhdl
+++ b/core_tb.vhdl
@@ -14,12 +14,6 @@ architecture behave of core_tb is
 
        -- testbench signals
        constant clk_period : time := 10 ns;
-
-        -- Dummy DRAM
-       signal wb_dram_in : wishbone_master_out;
-       signal wb_dram_out : wishbone_slave_out;
-       signal wb_dram_ctrl_in : wb_io_master_out;
-       signal wb_dram_ctrl_out : wb_io_slave_out;
 begin
 
     soc0: entity work.soc
@@ -27,19 +21,11 @@ begin
            SIM => true,
            MEMORY_SIZE => (384*1024),
            RAM_INIT_FILE => "main_ram.bin",
-           RESET_LOW => false,
            CLK_FREQ => 100000000
            )
        port map(
            rst => rst,
-           system_clk => clk,
-           uart0_rxd => '0',
-           uart0_txd => open,
-           wb_dram_in => wb_dram_in,
-           wb_dram_out => wb_dram_out,
-           wb_dram_ctrl_in => wb_dram_ctrl_in,
-           wb_dram_ctrl_out => wb_dram_ctrl_out,
-           alt_reset => '0'
+           system_clk => clk
            );
 
     clk_process: process
@@ -60,12 +46,4 @@ begin
 
     jtag: entity work.sim_jtag;
 
-    -- Dummy DRAM
-    wb_dram_out.ack <= wb_dram_in.cyc and wb_dram_in.stb;
-    wb_dram_out.dat <= x"FFFFFFFFFFFFFFFF";
-    wb_dram_out.stall <= '0';
-    wb_dram_ctrl_out.ack <= wb_dram_ctrl_in.cyc and wb_dram_ctrl_in.stb;
-    wb_dram_ctrl_out.dat <= x"FFFFFFFF";
-    wb_dram_ctrl_out.stall <= '0';
-
 end;