-- testbench signals
constant clk_period : time := 10 ns;
-
- -- Dummy DRAM
- signal wb_dram_in : wishbone_master_out;
- signal wb_dram_out : wishbone_slave_out;
begin
soc0: entity work.soc
SIM => true,
MEMORY_SIZE => (384*1024),
RAM_INIT_FILE => "main_ram.bin",
- RESET_LOW => false
+ CLK_FREQ => 100000000
)
port map(
rst => rst,
- system_clk => clk,
- uart0_rxd => '0',
- uart0_txd => open,
- wb_dram_in => wb_dram_in,
- wb_dram_out => wb_dram_out,
- alt_reset => '0'
+ system_clk => clk
);
clk_process: process
jtag: entity work.sim_jtag;
- -- Dummy DRAM
- wb_dram_out.ack <= wb_dram_in.cyc and wb_dram_in.stb;
- wb_dram_out.dat <= x"FFFFFFFFFFFFFFFF";
- wb_dram_out.stall <= wb_dram_in.cyc and not wb_dram_out.ack;
-
end;