-- testbench signals
constant clk_period : time := 10 ns;
-
- -- Dummy DRAM
- signal wb_dram_in : wishbone_master_out;
- signal wb_dram_out : wishbone_slave_out;
- signal wb_dram_ctrl_in : wb_io_master_out;
- signal wb_dram_ctrl_out : wb_io_slave_out;
begin
soc0: entity work.soc
)
port map(
rst => rst,
- system_clk => clk,
- wb_dram_in => wb_dram_in,
- wb_dram_out => wb_dram_out,
- wb_dram_ctrl_in => wb_dram_ctrl_in,
- wb_dram_ctrl_out => wb_dram_ctrl_out
+ system_clk => clk
);
clk_process: process
jtag: entity work.sim_jtag;
- -- Dummy DRAM
- wb_dram_out.ack <= wb_dram_in.cyc and wb_dram_in.stb;
- wb_dram_out.dat <= x"FFFFFFFFFFFFFFFF";
- wb_dram_out.stall <= '0';
- wb_dram_ctrl_out.ack <= wb_dram_ctrl_in.cyc and wb_dram_ctrl_in.stb;
- wb_dram_ctrl_out.dat <= x"FFFFFFFF";
- wb_dram_ctrl_out.stall <= '0';
-
end;