Add Tercel PHY reset synchronization

[microwatt.git] / countzero_tb.vhdl

diff --git a/countzero_tb.vhdl b/countzero_tb.vhdl
index 91de3342e984b5a9ed84c00194244b5cfa44d032..42f6048e7543d92f9490f9b8bfb204c04fc497a7 100644 (file)
--- a/countzero_tb.vhdl
+++ b/countzero_tb.vhdl
@@ -15,16 +15,26 @@ architecture behave of countzero_tb is
     signal is_32bit, count_right: std_ulogic := '0';
     signal result: std_ulogic_vector(63 downto 0);
     signal randno: std_ulogic_vector(63 downto 0);
+    signal clk: std_ulogic;
 
 begin
     zerocounter_0: entity work.zero_counter
        port map (
+            clk => clk,
            rs => rs,
            result => result,
            count_right => count_right,
            is_32bit => is_32bit
        );
 
+    clk_process: process
+    begin
+        clk <= '0';
+        wait for clk_period/2;
+        clk <= '1';
+        wait for clk_period/2;
+    end process;
+
     stim_process: process
         variable r: std_ulogic_vector(63 downto 0);
     begin
@@ -99,7 +109,6 @@ begin
             end loop;
         end loop;
 
-        assert false report "end of test" severity failure;
-        wait;
+       std.env.finish;
     end process;
 end behave;