Add Tercel PHY reset synchronization

[microwatt.git] / cr_file.vhdl

diff --git a/cr_file.vhdl b/cr_file.vhdl
index 37fa76b2378706f77c42776b1078bc0ff00415d4..3e6566378596249ebbded8e0ad5941b4f359793f 100644 (file)
--- a/cr_file.vhdl
+++ b/cr_file.vhdl
@@ -7,7 +7,9 @@ use work.common.all;
 
 entity cr_file is
     generic (
-        SIM : boolean := false
+        SIM : boolean := false;
+        -- Non-zero to enable log data collection
+        LOG_LENGTH : natural := 0
         );
     port(
         clk   : in std_logic;
@@ -29,7 +31,6 @@ architecture behaviour of cr_file is
     signal crs_updated : std_ulogic_vector(31 downto 0);
     signal xerc : xer_common_t := xerc_init;
     signal xerc_updated : xer_common_t;
-    signal log_data : std_ulogic_vector(12 downto 0);
 begin
     cr_create_0: process(all)
         variable hi, lo : integer := 0;
@@ -91,14 +92,18 @@ begin
         end process;
     end generate;
 
-    cr_log: process(clk)
+    cf_log: if LOG_LENGTH > 0 generate
+        signal log_data : std_ulogic_vector(12 downto 0);
     begin
-        if rising_edge(clk) then
-            log_data <= w_in.write_cr_enable &
-                        w_in.write_cr_data(31 downto 28) &
-                        w_in.write_cr_mask;
-        end if;
-    end process;
-    log_out <= log_data;
+        cr_log: process(clk)
+        begin
+            if rising_edge(clk) then
+                log_data <= w_in.write_cr_enable &
+                            w_in.write_cr_data(31 downto 28) &
+                            w_in.write_cr_mask;
+            end if;
+        end process;
+        log_out <= log_data;
+    end generate;
 
 end architecture behaviour;